M01500 - SEMI M15 - Polished Wafer Defect Limits Table for Semi-Insulating Gallium Arsenide Wafers StdPbc-0615 SEMI C19-0708 (technical revision)

SEMI C19-0708 (technical revision)

11-1106 (technical revision)

a definition of the wafer transport plane within process modules is required

and the responsibility of consumers to assess particular implementations for use in their factories

This Standard applies to all documentation provided by the equipment supplier to the equipment purchaser for new semiconductor

M01500 - SEMI M15 - Polished Wafer Defect Limits Table for Semi-Insulating Gallium Arsenide Wafers StdPbc-0615 SEMI C19-0708 (technical revision)This document defines the maximum number of defects, by type, that an acceptable polished Semi Insulating Gallium Arsenide (GaAs) wafer may exhibit. Referenced SEMI Standards None.