CD4027 - Dual JK Flip Flop Peltier x1 Brown x10 Red x100

x1 Brown x10 Red x100 Orange x1000 Yellow x10000 Green x100000 Blue x1000000 Violet x10000000 Grey x100000000 White x1000000000

A LOW at the parallel enable input (PE) disables the counting action and causes the data at thedata inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock

Color: Gold

Few external components

5%(85% measuring range) Repeatability: <±5

CD4027 - Dual JK Flip Flop Peltier x1 Brown x10 Red x100Introduction : CD4027 Dual JK Flip Flop monolithic complementary MOS (CMOS) integrated circuits constructed with N and P channel enhancement mode transistors. Each flip flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip flops are edge sensitive to the clock input and change state on the positive going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high